To understand the basics of the shift register, I recommend viewing the VHDL tutorial about the std_logic_vector. Every time a new element enters the queue, it shifts the existing ones one place further away from the input. You can dramatically reduce the number of consumed resources by choosing the right shift register implementation for your needs and FPGA architecture.Ī shift register implements a FIFO of fixed length. There are many ways to create a shift register in VHDL, though not all of them are equal.
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